Semiconductor components comprising flip-chip contacts are subject to new problems as a result of the development of new electrical materials for semiconductor wafers. These so-called “low-k materials” enable insulation thicknesses of less than 100 nanometers on semiconductor wafers having a diameter of 300 millimeters. Compared with the traditional thermal gate oxides, the new materials, on account of their extremely low dielectric constant, which is lower than the dielectric constant of silicon dioxide, are able to realize even thinner gate dielectrics for the same dielectric strength, with the result that improved properties become possible for semiconductor components of this type. Layer sequences for wiring structures on semiconductor chips can also be produced more compactly with low-k materials.
One disadvantage of these semiconductor components with insulation layers of “low-k material” however, is that the risk of delamination of such layers under thermal loading is significantly higher than in the case of the conventional insulation layers made of thermal silicon oxide and/or silicon nitride layers on silicon semiconductor wafers. In addition to the risk of delamination, while these new materials are softer and more spongy or more porous than previous insulation materials, they exhibit an increased brittleness that reduces the possibility of stress loading after a breaking loading.
The problems with new “low-k” insulation materials are also exacerbated by the environmental protection requirements for avoiding soft lead-containing solder materials for flip-chip contacts and replacing the solder materials by harder, lead-free solders whose flow temperature of 210° C. to 250° C. is significantly higher than in the case of the previously-used flip-chip contacts made of lead-containing solder materials, which undergo transition to the flow state at a temperature as low as 150°. Attempts to compensate for the increased risk of delamination and breaking of the new insulation layer materials by means of underfill materials that are arranged between a semiconductor chip with flip-chip contacts and a circuit substrate and have a reduced modulus of elasticity have not, however, heretofore achieved the desired success and the desirable reliability for flip-chip contacts made of lead-free solder material.
The problems that occur with conventional components comprising flip-chip contacts are illustrated by FIGS. 7 to 9. In this respect, FIG. 7 shows a schematic cross section through a semiconductor component comprising flip-chip contacts of conventional design, at temperatures below room temperature. FIG. 8 shows a schematic cross section through the semiconductor component in accordance with FIG. 7 at room temperature. FIG. 9 shows a schematic cross section through the semiconductor component in accordance with FIG. 8 above room temperature.
At temperatures below room temperature, as shown in FIG. 7, warping occurs in the case of conventional semiconductor components 10 on account of the different coefficients of thermal expansion of the semiconductor chip 4 and of the wiring substrate 12. The warping can be compensated for only in part by means of an underfill material 17 in the interspace 16 having a high modulus of elasticity. At room temperature, by contrast, the thermal strains are low, with the result that warping effects and shear stresses are minimized, as shown in FIG. 8. At temperatures above room temperature, the wiring substrate 12 expands to a greater extent than the semiconductor chip 4, with the result that the flip-chip contacts 2 are subjected to shear stress, and warping can also occur despite the underfill material 17.